UoP announces PG diploma course in IC layout design
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The University of Pune is starting a new PG diploma course in IC layout design, offering integration with intellectual property protection. It will be India's first government institution to offer an integrated course in LC layout design. The course is slated to begin on December 3.
The official website of the Department of Electronic Science (DoES) said that a survey of major educational institutions offering courses related to VLSI design indicate these to be dominantly on the IC design methodology and design approaches. No institute has an IC layout design course in totality. Hence, there is a dire need for an evolving and dedicated UG/PG programme which offers technical exposure in IP matters and Layout Design fields.
On November 5, Dr A D Shaligram, HOD, DoES, had arranged a meeting of representatives of industrial and academic fields on this subject.
Y S Tanwar, registrar and founding registrar of semiconductor IC layout design registry, New Delhi, attend and spoke about the use of intellectual property protection for semiconductor field, highlighting government of India's efforts in intellectual property protection.
The 10-month specialised course includes five theory papers, practicals and one project.
The project could be either at the VLSI industry or at the University using the industry standard IC design tools available at the department.
The course will see an intake of 40 students through an entrance exam that is scheduled on November 24. Further details are available on the university website.
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